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S1D13513

S1D13513 Product Brief v2.2.pdf

S1D13513 XGA External SDRAM Display Controller 

SEC LCDC English page


The S1D13513 is a highly integrated display controller capable of supporting up to XGA TFT LCD panels. With the flexibility of an external SDRAM memory interface, this low cost, low power device supports a wide range of CPUs, panels, and a camera port. The S1D13513 feature set and architecture are designed to meet the requirements of today’s embedded markets. 

The S1D13513 features both sprite and 2D BitBLT engines designed to reduce the load on the host, while increasing the performance of graphics intensive operations. Additionally, the S1D13513 offers such features as multiple windows, alpha blending, gamma correction, and mirror/rotation functions which allow user configurability of various images on the Main/PIP1/PIP2 displays. The S1D13513's impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications. 

NOTE: S2D13513 is also available and meets automotive specifications. 


FEATURES 

.Direct and indirect CPU interfaces


.Serial host interface


.Memory interface for x16 or x32 externalSDRAM (x32 available on S1D13513 PBGAonly)


.Programmable resolutions and color depths


.Support for single RGB panel with serialcommand interface


.Clocks can be selected from two embeddedPLLs or digital clock input


.Two Crystal inputs


.Dual port camera i/f with resize function


.Sprite engine


.2D hardware acceleration engine


.Overlay features


.Gamma correction


.4-channel PWM for backlight control


.Keypad interface with 5x5 matrix support


.Software initiated power save mode


.COREVDD: 1.8V, IOVDD: 3.3V


.Package: PBGA 256-pin and QFP 208-pin(QFP does not support all features)




SYSTEM BLOCK DIAGRAM 












DESCRIPTION 

External Display Buffer 

.Uses external SDRAM or mobile SDRAM as display buffer


.Supports x16 / x32 SDRAM interface (size: 8 MB, 16 MB,32 MB or 64 MB) (x32 and 32/64 MB not supported forQFP package)


.SDRAM clock: 100MHz maximum



Display Support 

.Example resolutions


o1024x768@16bpp (x32 SDRAM only)


o800x600@16bpp (x32 SDRAM only)


o640x480@ 32bpp (x32 SDRAM only)



.RGB interface single panel


o16/18/24-bit color TFT(24-bit not supported on QFP)



.8-bit mono/color passive panels


.Color depths up to 32 bpp



Display Features 

.Multiple window (layer) support


.Mirror and 180° rotation functions


.Alpha blending


.Gamma correction


.Pseudo color expansion


.Hardware cursor support via the sprite engine


.Interrupts available:


oMaskable non-display (Vsync) interrupt


oDelayed version of Vsync Interrupt




Acceleration 

.2D BitBLT engine (read, write, move, and fill BLTs)


.2D sprite engine (up to 16 sprites)


.Unified command FIFO for both BitBLT and sprite



CPU Interface 

.Direct and indirect as well as serial host interface supportfor most popular CPU interfaces


.Registers are memory-mapped - M/R# input selectsbetween memory and register address space



Digital Video 

.Dual camera / video input port can be configured as 2x8-bit camera ports


oSupports resize function of the video in stream


oSupports raw JPEG capture from JPEG capablecamera



.Captures YUV data into SDRAM as YUV 4:2:2 format(Max. 16.6Mhz camera pixel clock)


.View image can be displayed to LCD


.Resize function built-in for both view and capture path



Miscellaneous 

.Internal system clock: 50MHz max. (half of SDRAM clock)


.4-channel PWM for backlight control


.I2C Interface (typically used for camera)


.Keypad Interface with 5 x 5 matrix support


.Software initiated power save mode


.Multiple general purpose input/output pins


.Flexible clock structure with two embedded PLLs:


oTwo embedded PLLS


oTwo built-in crystal inputs


oFour digital clock inputs


oClocks dynamically turned off when modules are notneeded



.COREVDD 1.8 volts and IOVDD 3.3 volts


.Operating Temperature: -40 to +85°C


.Package: PBGA 256-pin and QFP 208-pin




Document code: X78B-C-001-02.2 




http://global.epson.com/products/semicon 




NOTICE: 

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson.  Seiko Epson reserves the right to make changes to this material without notice.  Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes.  


All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies. 

.Seiko Epson Corporation 2006, 2017.  All rights reserved.


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